# FPGA Register Reference

Although the user has access to all FGPA registers, only those which provide user-accessible functionality are documented in this manual. Most FPGA registers in the full register map are reserved for Axsun internal purposes. FPGA registers with which a user might interact via the API are listed here:

| **Register#\[bit]** | **Description**                                    | **Notes (“0x” prefix indicates a hexadecimal value)**                                                                                                                                                                                                                                             |
| ------------------- | -------------------------------------------------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
| 2\[2] & 19\[15]     | Imaging control (Ethernet interface only)          | <p>both bits = 1 for Live Imaging</p><p>= 0 for Imaging Off </p><p>(control PCIe operation via <code>axImagingCntrlPCIe()</code> in <a href="/pages/-LP1lO3r3G1o4_eSgbOC">AxsunOCTCapture</a>)</p>                                                                                                |
| 2\[9, 11]           | Image\_sync input selection                        | See [Selecting the Image\_sync Input](/axsun-knowledge-base/ref-manual/gigabit-ethernet-daq-board/advanced-operation.md#selecting-the-image_sync-input)                                                                                                                                           |
| 20\[4]              | Raw data source selection                          | <p>= 1 for Test Vector raw data source</p><p>= 0 for ADC raw data source</p>                                                                                                                                                                                                                      |
| 20\[5, 13]          | Channel select                                     | See [Selecting which ADC Channel to Transmit](/axsun-knowledge-base/ref-manual/gigabit-ethernet-daq-board/advanced-operation.md#selecting-which-adc-channel-to-transmit)                                                                                                                          |
| 20\[6]              | Windowing function load applies to both channels   |                                                                                                                                                                                                                                                                                                   |
| 20\[14]             | Real/Imaginary select for windowing function load  | See [Dispersion Compensation](/axsun-knowledge-base/ref-manual/gigabit-ethernet-daq-board/advanced-operation.md#dispersion-compensation)                                                                                                                                                          |
| 23\[15..0]          | Offset                                             | See [Offset and Gain](/axsun-knowledge-base/ref-manual/gigabit-ethernet-daq-board/advanced-operation.md#setting-gain-and-offset-for-dynamic-range-compression)                                                                                                                                    |
| 24\[15..0]          | Gain                                               | See [Offset and Gain](/axsun-knowledge-base/ref-manual/gigabit-ethernet-daq-board/advanced-operation.md#setting-gain-and-offset-for-dynamic-range-compression)                                                                                                                                    |
| 25\[15..0]          | Windowing function                                 | Write 2048 consecutive U16 values representing the windowing function (Real or Imaginary depending on Reg 20 \[bit 14]). See [Setting the Apodization Window Function](/axsun-knowledge-base/ref-manual/gigabit-ethernet-daq-board/advanced-operation.md#setting-the-apodization-window-function) |
| 26\[15..0]          | Test Vector                                        | Write 2048 consecutive U16 values representing the desired test vector.  (Enable Reg 20\[4] to turn on Test Vector raw data source)                                                                                                                                                               |
| 30\[15..0]          | Pre-FFT Background Subtraction                     | Write 2048 consecutive I16 values representing the background signature.  See [Background Subtraction](/axsun-knowledge-base/ref-manual/gigabit-ethernet-daq-board/advanced-operation.md#background-subtraction).                                                                                 |
| 31\[0]              | Burst Record control (Ethernet interface only)     | <p>= 1 for Burst Record imaging ON </p><p>= 0 for Burst Record OFF </p><p>(control PCIe operation via <code>axImagingCntrlPCIe()</code> in <a href="/pages/-LP1lO3r3G1o4_eSgbOC">AxsunOCTCapture</a>)</p>                                                                                         |
| 33\[15..0]          | Burst Record # of images (Ethernet interface only) | See [Operational Modes](/axsun-knowledge-base/ref-manual/gigabit-ethernet-daq-board/basic-operation.md#live-imaging-burst-record)                                                                                                                                                                 |
| 37\[15..0]          | Post-FFT Background Subtraction                    | Write 1024 consecutive U16 values representing the background signature.  See [Background Subtraction](/axsun-knowledge-base/ref-manual/gigabit-ethernet-daq-board/advanced-operation.md#background-subtraction).                                                                                 |
| 60\[15..0]          | Sub-sampling Factor                                | The desired Subsampling Factor minus one (M-1).  See [Raw Data / Bypass Modes and A-line Subsampling](/axsun-knowledge-base/ref-manual/gigabit-ethernet-daq-board/advanced-operation.md#raw-data-bypass-modes-and-a-line-subsampling)                                                             |
| 61\[15..0]          | Bypass Select                                      | Write two consecutive values according to [Bypass Modes table](https://axsun.gitbook.io/axsun-technologies-knowledge-base/ref-manual/gigabit-ethernet-daq-board/advanced-operation#raw-data-bypass-modes-and-a-line-subsampling)                                                                  |


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