The Camera Link Data Acquisition Board (CLDAQ) is designed to allow users of the OEM version of the SS-OCT engine to collect data at a speed of up to 500 MSamples/s with 12-bit resolution. The Camera Link configuration is base with 83.33 MHz and 24 bit pixel data.
For the trigger and clock, connect using a SATA cable the laser board and the DAQ board as shown in the figure below.
For the data signal, connect using a SATA cable the balanced receiver board and the DAQ board as shown in the figure below.
Connect the power adapter cable into the power connectors on the laser board and the DAQ board.
Connect the light source to the computer via USB cable.
Connect the Camera Link DAQ to the computer via USB cable.
Connect the Camera Link socket on the DAQ board and your computer's frame grabber board.
Open OCT Host application
Press Acquire to start collecting data. The ADC State indicator will display green.
Press Standby to stop acquiring data. The Uptime field indicates the period of time (in seconds) that the ADC card has been collecting data.
The laser engine usually ships with the most updated camera link DAQ firmware and FPGA bitsream firmware. In some cases, Tech Support migh recommend updating one of both of these firmwares. The camera link DAQ firmware can be updated per these instructions. The FPGA bitsream firmware can be updated per these instructions.
The FPGA settings, stored in flash, are loaded into the FPGA at start up.
The 4 controls allow reading and writing FPGA settings
Send to Device sends the FPGA settings to the ADC board, writes them to the FPGA and saves them so that they are re-loaded at power up
Request from Device reads the FPGA settings from the ADC board
Load from Disk loads FPGA settings from a file on computer
Save to Disk saves the current parameters to computer
Get FPGA Registers gets the current values from all the FPGA registers
Set FPGA Register sets the value for one register. This settings is not saved to flash and is not remembered when the system is rebooted. To edit a value enter the register number in Register text box and value in Value text box then press Set.
The Acquire and Standby controls in the Cameralink FPGA tab have the same function as the same controls in the Engine Control tab.
FW Rev Low (R/O)
[15:8] Minor revision,
[7:0] Development Revision (if different than 0)
FW Rev High (R/O)
[7:0] Major Revision
[11:8] Test Control,
 Trigger Select,
 Camera Link Power Enable,
 ADC Power Enable,
 FVAL Enable,
0000-Test Off(data routed from 12-bit ADC)
1000- Grayscale driven out Camera Link interface,
Trigger Select: 0 - sweep trigger, 1- LVAL for testing
[11:0] Active Pixel Count (default 1376)
[11:0] Active Line Count (default 512)
[11:0] Horizontal Blanking Count (default 292)
Note: A-Scan Length + Horizontal Blanking = 1668 (100 kHz)
[7:0] Vertical Blanking Count ( default 20)
Gray Level Control
 Complement Screen
[3:0] grayscale Step Size (default 8)
DAQ settings needs to be configured as such:
Line Lengths Pixels = 1376 (number of samples per A-scan)
Vertical Line Count = 1 (Line scan mode)
Horizontal Blank Count = 500 ( 1 Count corresponds to 6 ns)
Vertical Blank Count = 0 (Line scan mode)
Matrox Solios frame grabber set up as following:
camera type= Line scan
Pixel clock frequency = 83.33 MHz
Image size X = 688 (always half the Line Length Pixel size of the DAQ)
Image size Y = 500