FPGA Register Reference

Although the user has access to all FGPA registers, only those which provide user-accessible functionality are documented in this manual. Most FPGA registers in the full register map are reserved for Axsun internal purposes. FPGA registers with which a user might interact via the API are listed here:

Register#[bit]

Description

Notes (“0x” prefix indicates a hexadecimal value)

2[2] & 19[15]

Imaging control (Ethernet interface only)

both bits = 1 for Live Imaging

= 0 for Imaging Off

(control PCIe operation via axImagingCntrlPCIe() in AxsunOCTCapture)

2[9, 11]

Image_sync input selection

20[4]

Raw data source selection

= 1 for Test Vector raw data source

= 0 for ADC raw data source

20[5, 13]

Channel select

20[6]

Windowing function load applies to both channels

20[14]

Real/Imaginary select for windowing function load

23[15..0]

Offset

24[15..0]

Gain

25[15..0]

Windowing function

Write 2048 consecutive U16 values representing the windowing function (Real or Imaginary depending on Reg 20 [bit 14]). See Setting the Apodization Window Function

26[15..0]

Test Vector

Write 2048 consecutive U16 values representing the desired test vector. (Enable Reg 20[4] to turn on Test Vector raw data source)

30[15..0]

Pre-FFT Background Subtraction

Write 2048 consecutive I16 values representing the background signature. See Background Subtraction.

31[0]

Burst Record control (Ethernet interface only)

= 1 for Burst Record imaging ON

= 0 for Burst Record OFF

(control PCIe operation via axImagingCntrlPCIe() in AxsunOCTCapture)

33[15..0]

Burst Record # of images (Ethernet interface only)

37[15..0]

Post-FFT Background Subtraction

Write 1024 consecutive U16 values representing the background signature. See Background Subtraction.

60[15..0]

Sub-sampling Factor

The desired Subsampling Factor minus one (M-1). See Raw Data / Bypass Modes and A-line Subsampling

61[15..0]

Bypass Select

Write two consecutive values according to Bypass Modes table

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