Check that the Requested Image # control is set to
-1. This value returns the most recently captured image, rather than a previously captured and uniquely numbered image which is returned when this control is set to a non-zero positive value.
The image width is determined by the period of the Image_sync synchronization pulse. Check that the Image_sync connection to the DAQ board is robust and has a constant period. Also check that the correct Image_sync input (LVCMOS, LVDS, or internal) is selected in FPGA register 2, bits 9 and 11 .
Use the Image Capture Tool's LOAD button on the Buffer tab, or use the
axLoadFile(..)API command in AxsunOCTCapture.dll.
Buffer files saved using the Image Capture Tool or the
axSaveFile(..)API command use a custom format which includes the image data as well as other metadata and are only interpretable by the Capture API.
Each system produces a specific number of k-clock pulses based on the laser's wavelength tuning range and the k-clock configured scan depth. These k-clock pulses are used to directly control the sampling of the analog-to-digital converters and the number of samples typically falls between 1024 and 2048 (your system's exact value can be found on your laser test report). Because the Fourier transform computation requires input data with power-of-2 length, the sampled data is zero-padded from up to 2048 points in the same step as apodization/windowing and dispersion compensation. The Width (samples) setting is the number of valid points in the programmed window function (should be set = ) and then 2048– zeros are automatically appended to make the total number of points equal to 2048. If the Width(samples) setting is higher than the actual valid number of samples produced , then invalid or spurious samples may not be zeroed-out and will likely cause artifacts in the computed image.
Each A-line is computed by Fourier transforming an input vector with length of 2048. Due to symmetry properties of the Fourier transform, half of the resulting transformed data is redundant and thus the vector length in all subsequent processing blocks is truncated to 1024 pixels.
Mirroring artifacts at the top and bottom of images are common in Fourier Domain OCT. Mirroring at the top of the image comes from the complex conjugate property of the Fourier transform, and the mirroring at the bottom comes from aliasing (frequency content higher than Nyquist). These artifacts are not specific to the Axsun system; rather, any FD-OCT system employing an FFT (swept source or spectrometer-based) will exhibit these phenomena.
The maximum scan depth is fixed during system manufacturing and is based on the optical path length delay in the integrated k-clock interferometer. Reduction of the scan depth can be accomplished in software by simply cropping out regions from the generated images after they are retrieved into a client application.
The forced trigger warning is because there no Image_sync signal attached to the DAQ to synchronize it with scanner/probe. When no sync signal is found, the force trigger mode operates like an oscilloscope without a trigger, basically updating the screen with the most recently captured data in an asynchronous fashion. This is a normal operation until an Image_sync signal is connected to the DAQ.
If you are adjusting the dispersion compensation coefficients and window LUT function and the Auto Update switch is “on” then any incremental change will get immediately loaded to the DAQ, which takes some finite time. If you make too many rapid updates to these controls, it could queue up a bunch of updates that then take a lot of time to sequentially download. Try turning off Auto Update, make necessary changes, and then press “Update DAQ” to send the new window LUT in a singular step.
Use AxsunOCTControl_LW.dll if you are either creating an application for a non-Windows platform or are coding in a language other than C# and would like to avoid accessing AxsunOCTControl.dll through COM assembly registration.
Use AxsunOCTControl.dll if you are creating an application in C# or in a managed language which supports straightforward binding of Microsoft .NET assemblies on a 32- or 64-bit Windows platform.
The Ethernet interface enables compact system architectures and requires bandwidth reduction via A-line subsampling when using the Bypass Mode functionality to access upstream data during system integration, optimization, and debugging. Depending on your PC capabilities and resource usage from unrelated processes, Gigabit Ethernet speeds of approximately 800-900 Mbps are realizable with minimal or no packet loss.
On the other hand, the PCIe interface provides sufficient bandwidth to access Raw ADC Data at full A-line rate (without subsampling) but also requires to be plugged into the PCIe slot of a desktop or workstation PC, or alternatively requires the use of a Thunderbolt chassis.
You can either buy a second power supply, cord and power Y cable for powering up the PCIe DAQ separately or you can extend the existing power Y cable.