Hardware Control Tool
version 1.0.0.192 or later

Introduction

The Hardware Control Tool (AxsunHardwareControlTool.exe) is a Windows OS software interface for users of Axsun SS-OCT Laser Engine and DAQ products. It provides a tab- and button-based GUI to easily interact with a variety of features provided by Axsun Laser Engine and DAQ devices.
The Hardware Control Tool ("HWCT") connects to the device using the AxsunOCTControl API or AxsunOCTControl_LW API and supports communication over USB, RS-232, and Ethernet (depending on the device configuration).
The Hardware Control Tool is recommended for users of the Axsun Integrated Engine with Ethernet / PCIe DAQ. Its primary functions include:
  • configuring high-level Ethernet/PCIe DAQ features such as:
    • apodization window function and spectral shaping
    • dispersion compensation
    • pre-FFT and post-FFT background subtraction
    • processing pipeline bypass modes for raw data access
  • starting and stopping OCT swept laser emission
  • configuring K-clock delay and other power-on default settings
  • operating an optional motorized Variable Delay Line (VDL)
  • operating an optional visible aiming laser

Compatibility Requirements

PC: The Hardware Control Tool is compatible with 64-bit versions of Windows OS from Windows 7 through Windows 10. There are no special hardware requirements other than an available USB port (or RS-232 serial port) for each Axsun device, or a 1Gbps Ethernet port for connecting to the Ethernet DAQ via network interface.
FPGA bitstream: The Hardware Control Tool supports the full functionality in legacy versions of the FPGA bitstream, but some functionality provided in the HWCT is specific only to newer FPGA bitstream versions. Keep your FPGA version current to take advantage of new functionality.
Laser and DAQ Hardware: Some HWCT functions support optional features which must be installed or enabled on the system at time of manufacture. Your hardware may not support these functions.

Relationship to OCT Host

Both OCT Host and the Hardware Control Tool provide a command & messaging interface to Axsun hardware devices. Although they have some overlapping functionality, OCT Host is laser-centric and is intended to support debugging, field-service, and maintenance tasks, whereas the Hardware Control Tool is designed for users of the Axsun Ethernet/PCIe DAQ board and enables high-level interaction with advanced DAQ board features.
WARNING: Do not open OCT Host and the Hardware Control Tool concurrently. Ethernet DAQ hardware will accept only one network connection from a library instance at a time.

Installation

To install the Hardware Control Tool and its dependencies, download the most recent version from www.axsun.com/downloads and follow the complete software installation instructions for the Axsun Integrated Engine.

Using the Hardware Control Tool

NOTE: Your screen may not match exactly with the screen representations shown in this guide, depending on your system configuration and installed firmware/software versions.
Physically connect and power-up the Axsun devices. Launch AxsunHardwareControlTool.exe and wait for the main window to open:
Axsun Hardware Control Tool main window
Along with application & library version information, some introductory information about the intended behavior of the Hardware Control Tool is presented on the About tab:
  • Tip strips: Hovering the mouse cursor over buttons or indicators reveals additional information about their functionality or their associated AxsunOCTControl_LW.dll API method. Use Tip Strip information as hints to help you integrate the device functionality into your custom client application based on the AxsunOCTControl_LW library calls.
  • Indicator validity: Indicators in the Hardware Control Tool provide current status information about the device state only:
    • when the associated board is connected and listed successfully in the DEVICES list, and
    • after an indicator is refreshed using an associated READ button (i.e. changes are not necessarily event-driven or automatically polled; you must poll manually when an indicator refresh is desired).
  • Board reconfiguration: The Hardware Control Tool generally does not automatically confirm success or failure of requested configuration changes. It is good practice to inspect for the desired change in the transmitted image or in the associated indicator following a manual refresh. With few exceptions, device configuration changes will NOT persist after the board is reset via cycling power. Use the Power-On Defaults tab to configure a device's default behavior.

Connected Devices

Axsun devices (laser engines and DAQ boards) which are successfully connected to the Hardware Control Tool will always be listed along with their firmware (FW) version, FPGA version (DAQ board only), and interface type (Ethernet network, USB, or RS-232) in the upper left corner of the main Hardware Control Tool window:
Laser Engine and Ethernet DAQ devices connected to the Hardware Control Tool
If a physically connected and powered device is not listed, first try restarting the hardware by cycling its power. If connection difficulties persist, see USB Connection Problems or Ethernet DAQ Connection Problems on the Troubleshooting page to insure correct software configuration and installation.
NOTE: A DAQ connected via its PCIe interface can also be connected to the Hardware Control Tool via its USB or Ethernet interface. However, the PCIe connection is established via the Image Capture Tool GUI and the AxsunOCTCapture library. See the DAQ Architecture & Interface Background page for more information.

Laser Emission Controls & Indicator, Ethernet DAQ Imaging Mode Controls

LASER: ON and LASER: OFF buttons control the emission state of the laser.
EDAQ: LIVE, EDAQ: OFF, and EDAQ: RECORD buttons control the imaging modes of an Ethernet-connected DAQ (for DAQs using the PCIe interface, use the corresponding buttons in the Image Capture Tool). Refer to Controlling Operational Modes for more details on the DAQ behavior controlled by these buttons.
Laser emission status is shown by the green indicator next to the laser emission control buttons.
Laser emission is ON as shown by the bright green indicator color.

Feature Group Tabs

Additional Hardware Control Tool features are grouped onto tabs which are arranged horizontally under the Connected Devices indicator. The following sections highlight the relevant controls and indicators available on each tab. Descriptions of functionality are often written near the relevant control directly on the tab. Additional information can be found in the documentation for the underlying API functions in the AxsunOCTControl or AxsunOCTControl_LW libraries.
  • Click on a tab's title to activate it in the foreground:
Titles of the Feature Group Tabs in the Hardware Control Tool

Miscellaneous

Control or Indicator Name
AxsunOCTControl_LW Functions
AxsunOCTControl Functions
GO HOME
axHomeVDL()
HomeVDL()
VDL Position (mm)
axMoveAbsVDL()
MoveAbsVDL()
K-Clock Delay (ns)
axSetClockDelay()
SetClockDelay()
DAQ Timing Settings (Clock)
axSetSampleClockSource()
WriteDAQRegisterBit() as described in Advanced DAQ Features
DAQ Timing Settings (Sweep Trigger)
axSetSweepTriggerSource()
WriteDAQRegisterBit() as described in Advanced DAQ Features
DAQ Timing Settings (Image_sync)
axSetImageSyncSource()
WriteDAQRegisterBit() as described in Advanced DAQ Features
Listen for Network Devices
axNetworkInterfaceOpen()
StartNetworkControlInterface() and StopNetworkControlInterface()
Visible Aiming Laser ON/OFF
axSetPointerEmission()
FPGA Resampling Phase Multiplier
FPGA Resampling Clock Delay
  • The Listen for Network Devices toggle switch selects whether or not the Hardware Control Tool application will listen for (and establish & maintain a control connection with) an Ethernet DAQ present on the host computer's network interface. If this switch is OFF, control connections require the USB interface. Disabling the network-based control interface is for installations wherein an Ethernet DAQ is connected via Ethernet for high-bandwidth data capture only (using AxsunOCTCapture) but USB is the desired control interface for low-bandwidth command and status messaging.
  • Controls related to a Variable Delay Line (VDL), Visible Aiming Laser emission, and FPGA Resampling are only functional for systems which have these optional features installed or enabled. Contact Axsun for more details.
  • The Use AxsunOCTControl_LW (requires restart) toggle switch selects whether the Hardware Control Tool application will load the AxsunOCTControl_LW library (switch = ON) or the AxsunOCTControl library (switch = OFF) the next time it is launched. (The currently-loaded library and version is shown in the Control Library & Version: indicator at the bottom of the About tab.)
The Miscellaneous tab

Pipeline Modes & Subsampling

The Pipeline Modes & Subsampling tab selects the location from which captured data is transmitted to the host interface from within the DAQ's FPGA-based SS-OCT image processing pipeline. Data is available in raw format directly from the ADC (or "Test Vectors"), in fully-processed intensity SS-OCT image format, or at intermediate steps within the processing pipeline.
NOTE: Depending on the connected data capture interface (i.e. Ethernet or PCIe), A-line Subsampling may be required to prevent saturating the interface's data bandwidth. See Advanced DAQ Features for more information.
The Pipeline Modes & Subsampling tab
Control or Indicator Name
AxsunOCTControl_LW Functions
AxsunOCTControl Functions
Subsampling Factor (1 of N)
axSetSubsamplingFactor()
SetFPGARegister()as described in Advanced DAQ Features
Offset
axSetEightBitOffset()
SetFPGARegister()as described in Advanced DAQ Features
Gain
axSetEightBitGain()
SetFPGARegister()as described in Advanced DAQ Features
Raw Data Source
(ADCs or Test Vectors)
axSetFPGARegisterSingleBit() as described in Advanced DAQ Features
WriteDAQRegisterBit() as described in Advanced DAQ Features
Colored Pipeline Mode diagram buttons
axSetPipelineMode()
SetFPGARegister()as described in Advanced DAQ Features
  • Colored buttons to select a DAQ Pipeline Bypass Mode are oriented horizontally in a left-to-right fashion representing the data flow direction through the SS-OCT data processing pipeline implemented in the FPGA. These buttons configure the DAQ to transmit captured data to the host interface directly from the output of the selected processing block with all upstream blocks to the left enabled, and all downstream blocks to the right 'bypassed'.
    • BLUE buttons select Channel 1 (H) only,
    • RED buttons select Channel 2 (V) only,
    • PURPLE buttons select the vector sum of Channels 1 and 2 (i.e. polarization diverse mode), and
    • PINK buttons select both Channels 1 and 2 concurrently.
NOTE: The right-most JPEG block is non-functional when using the DAQ's PCIe interface. JPEG image compression is available only for Ethernet-connected DAQs where data bandwidth reduction is desirable.
NOTE: It is not possible to access both Channels 1 and 2 concurrently when using JPEG compression on an Ethernet DAQ.
  • Choose A-line Subsampling approach is a menu which configures the Hardware Control Tool to automatically program a A-Line Subsampling behavior specific to each subsequently selected Pipeline Bypass Mode:
    • Set Manually does not change subsampling. Use the Subsampling Factor (1 of N) control.
    • No Subsampling turns subsampling off resulting in maximum bandwidth (which may saturate the data interface in some situations).
    • Automatic (Aggressive) keeps bandwidth considerably under the maximum limit for all interfaces.
    • Automatic (Max GigE BW) sets subsampling appropriate for the maximum bandwidth supported by the Gigabit Ethernet interface for a 100 kHz laser.
    • Automatic (100kHz PCIe) sets subsampling appropriate for the maximum bandwidth supported by the PCIe interface for a 100 kHz laser.
    • Automatic (200kHz PCIe) sets subsampling appropriate for the maximum bandwidth supported by the PCIe interface for a 200 kHz laser.
A-line Subsampling approach selection

Windowing & Dispersion Compensation

The Windowing & Dispersion Compensation tab provides the ability to upload a complex-valued apodization window function "lookup-table" (LUT) which the DAQ's FPGA multiplies by every subsequently acquired A-scan. Plots show the real and imaginary components of the loaded window functions in each of the two ADC channels.
  • Any selections or updates made in the Ch 1 Windowing LUT Setup control will be immediately uploaded to the DAQ and applied to the Channel 1/H data stream.
  • If the Ch 2 Window ___ from Ch 1 control is set to Copy, the Ch 1 window function will also be uploaded to the DAQ and applied to the Channel 2/V data stream.
  • If the Ch 2 Window ___ from Ch 1 control is set to Independent, any selections or updates made in the Ch 2 Windowing LUT Setup control will be immediately uploaded to the DAQ and applied to the Channel 2/V data stream.
The Windowing & Dispersion Compensation tab
  • The Type menu provides several commonly used window function types which allow the user to trade off between side lobe suppression and PSF width by affecting the magnitude of the complex-valued window function.
  • Width (samples) should be set depending on the laser and K-clock parameters as provided on individual laser test reports. Acquired data points after the value selected in Width (samples) are zero-padded out to 2048 samples. The value depends on the tuning bandwidth and the scan depth configured for a specific laser.
  • Coefficients a1, a2, and a3 are the linear, quadratic, and cubic coefficients in a Taylor series polynomial expansion of the phase of the complex-valued window function and can be used to digitally compensate for dispersion in the OCT interferometer.
  • If you wish to apply no window function at all, select "Ones" from the Type menu (i.e. constant unity magnitude) and set all "Coefficient a_" values to 0.0 (i.e. zero phase adjustment).
HINT: Observe the effects of updating the windowing LUT in real-time by watching for changes in the live image display using the Image Capture Tool.

Background Subtraction

The Background Subtraction tab provides controls for both Pre-FFT background subtraction and Post-FFT background subtraction in the image processing pipeline. Background subtraction works via uploading a "lookup-table" (LUT) of the same length as the A-scan data which the FPGA then subtracts from every subsequently acquired A-scan on a sample-by-sample basis.
  • DISABLE turns background subtraction off (sets all LUT values to zero).
  • LOAD FROM FILE... displays a file dialog which can be used to load a background subtraction LUT from disk and upload it to the FPGA.
The Background Subtraction tab

Pre-FFT DC Offsets

In addition to the LUT-based background subtraction, the FPGA can also subtract a constant offset from all samples in the A-scan, in order to compensate for small DC offsets inherent in each of the ADC channels. This subtraction is performed before all other image processing steps.
  • Adjust the Pre-FFT DC Offsets independently for Ch 1 and Ch 2 until the DC frequency content in post-FFT transmitted data is minimized.
Control or Indicator Name
AxsunOCTControl_LW Functions
AxsunOCTControl Functions
Pre-FFT DC Offsets (Ch 1)
axSetFPGARegisterSingleByte() to set high (most significant) byte of Reg 39
SetFPGARegister()to set high byte of Reg 39
Pre-FFT DC Offsets (Ch 2)
axSetFPGARegisterSingleByte() to set low (least significant) byte of Reg 39
SetFPGARegister()to set low byte of Reg 39

FPGA Registers

The FPGA Registers tab is for low-level access (reading & writing) to the primary control interface for the Axsun Ethernet/PCIe DAQ FGPA: its control and status registers.
NOTE: Most DAQ FPGA functionality is exposed in the Hardware Control Tool GUI with high level feature-specific buttons and indicators (and in the AxsunOCTControl_LW or AxsunOCTCapture libraries with higher level feature-specific API calls), so user interaction with the low-level controls on this tab should be rare except in cases of advanced configuration.
The FPGA Registers tab
  • The READ ALL REGISTERS button can be used to query all FPGA registers (numbered 0 to 95) and refresh the table of current values (provided in both hexadecimal and decimal notation). Values which have changed since the last refresh will be highlighted in red.
  • Depending on a given register's interpretation, updating an FPGA register value can be more convenient in either hexadecimal or decimal notation. Select a register number in the Reg# field, enter a value in the Hex Value or Dec Value field, and then press the corresponding WRITE button to update the register. Multiple fields are provided for convenience while re-entering the same register number/value combinations repeatedly.
  • For those control registers interpreted as a bitfield, it is convenient to set or clear a single control bit directly, without having to "read-modify-write" the entire 16-bit register value. Use the Write (single bit) control to select a register number, a bit number (from 0 to 15), and then press the corresponding SET or CLR (clear) button to change the bit state as desired:
Set or clear a single bit in a bitfield register.
  • For those control registers interpreted as an array or lookup-table (LUT), the desired sequence of array values can be entered into the Write (array) control by copying to the clipboard in a spreadsheet application and then pasting from the clipboard by pressing From Clipboard, or by loading directly from disk by pressing the From CSV File... button. Once pasted or loaded, either one or both columns of values will be displayed for visual verification or manual modification if necessary. Enter the target register number(s) in the Reg# fields (the two fields correspond to the two columns of array values) and then press the associated WRITE button to upload the array(s):
Write an array of values to a target FPGA register
HINT: Right-click the mouse cursor on the array indicator border or on individual elements for additional interactivity with the values in the array, such as inserting or deleting rows or columns:
The following table shows correspondence between buttons on the HWCT user interface and associated API methods to perform FPGA register reads and writes. Note that the Image Capture Tool and AxsunOCTCapture API can also read and write registers if connected via the PCIe interface.
Control or Indicator Name
AxsunOCTControl_LW
Functions
AxsunOCTControl Functions
READ ALL REGISTERS
Loop using axGetFPGARegister() or useaxGetFPGARegisterRange()
Loop using GetFPGARegister()
WRITE (full register)
axSetFPGARegister()
SetFPGARegister()
Write (single bit)
axSetFPGARegisterSingleBit()
WriteDAQRegisterBit()
Write (array)
Loop using axSetFPGARegister() or useaxSetFPGADataArray()
Loop using SetFPGARegister() or use SendFPGAData()
n/a *
axSetFPGARegisterSingleByte()
n/a *
axSetFPGARegisterSingleNibble()
n/a *
axSetFPGARegisterMasked()
* the HWCT user interface does not expose buttons for these special AxsunOCTControl_LW methods but they are available for convenience when integrating this API.

Power-On Defaults

Controls on the Power-On Defaults tab interact with the laser's or DAQ board's non-volatile memory which stores the default behavior to be applied when the device powers-on. Selected settings will persist until explicitly changed again.
The Power-On Defaults tab

LASER

  • The OCT Swept Laser Emission menu has three possible behaviors. Select a behavior from this menu to update the connected laser engine's non-volatile memory:
    • OFF at power-up: swept laser emission will never be turned on at power-up
    • Use Digital Input: the state of Pin 1 on the engine's Aux & Interlock connector will control swept laser emission
    • ON at power-up: swept laser emission will always be automatically turned on at power-up
  • The Aiming Laser Emission menu has three possible behaviors. If your engine has an optional aiming laser installed, select a behavior from this menu to update the connected laser engine's non-volatile memory:
    • OFF at power-up: aiming laser emission will never be turned on at power-up
    • Link to swept laser: aiming laser emission state will mirror that of the swept laser emission
    • ON at power-up: aiming laser emission will always be automatically turned on at power-up

DAQ FPGA REGISTER CONFIG SCRIPT

All DAQ functionality is controlled by a bank of FPGA registers which accept 16-bit values or bitfields. Power-on default behavior of the DAQ is determined using the "FPGA Configuration Script": a list of register-number/register-value pairs stored in non-volatile memory and written automatically in a consecutive fashion to the FPGA registers during board initialization.
The Power-On Defaults tab displays the currently loaded FPGA Config Script in a read-only indicator labeled DAQ's Configuration, and a similar indicator labeled Local Workspace is provided for interactive editing. The elements indicators display how many register-number/register-value pairs are currently in each indicator.
  • <-- COPY from DAQ copies the DAQ's current Config Script in non-volatile memory to the local workspace for editing.
  • WRITE to DAQ --> overwrites the DAQ's Config Script in non-volatile memory with the contents of the local workspace. Pressing this button is required to upload an edited Config Script. A board restart is required to execute the newly loaded script (i.e. during the next board initialization).
  • <-- LOAD from FILE... presents a file dialog to load an FPGA Config Script from disk into the Local Workspace.
  • --> SAVE to FILE... presents a file dialog to save an FPGA Config Script from the Local Workspace to disk (for creating a back-up copy or for editing in a spreadsheet application)
  • COPY to Local Workspace --> automatically creates register number/value entries in the Local Workspace based on the DAQ's current register state and the Windowing LUT(s) currently shown on the Windowing & Dispersion Compensation tab. This provides an easy way to generate a new Config Script in the Local Workspace based on the current DAQ behavior and loaded window function. (Pressing the WRITE to DAQ--> button is still required to the upload the new Config Script from the Local Workspace to the board.)
HINT: Use the --> SAVE to FILE... functionality to save a back-up copy of the original FPGA Config Script before uploading a new or modified Config Script. This will enable you to revert back to the original script if necessary, by using the <-- LOAD from FILE... functionality to open your back-up copy.

Test Vectors

The Axsun Ethernet/PCIe DAQ board can operate in an emulation mode wherein an arbitrary waveform can be loaded and then repeatedly substituted for sampled ADC data at the input to the imaging pipeline. The downstream FPGA processing and transmission of data to a host PC behaves equivalently to the standard (non-emulated) mode of operation.
This feature is convenient if optically-generated OCT signals or k-clocks are unavailable to the DAQ (e.g. no laser or interferometer connected). Data bandwidth, buffering mechanics, control interfaces, and API accesses are unchanged in emulation mode, and thus wholly relevant for purposes of software development & API integration, although the generated image is relatively static and uninteresting.
Waveforms for each channel are loaded as a "test vector" of length 2048 samples with 12-bits of dynamic range, just like real data generated by the analog-to-digital converters during normal operation. The Hardware Control Tool's Test Vectors tab provides an interface for selecting among several typical waveform types (sine, square, triangle, sawtooth) and parameters (amplitude, frequency, phase, DC offset) for each channel independently.
The Test Vectors tab
Waveforms are displayed in the corresponding plot and uploaded to the DAQ automatically when one of the Test Vector Setup values is changed.
Pseudo-gaussian noise of varying amplitude can also be added using the Test Vector Noise control. This simulated noise is introduced by the FPGA into an uploaded test vector and changes dynamically for each A-scan. As such, this noise is not displayed in the corresponding plot in the Hardware Control Tool even though it will be apparent in the subsequently transmitted image from the DAQ.
Without a laser engine connected to provide sample clocks and sweep triggers, the DAQ will also need to be configured to sample and trigger off of internal clock sources (e.g. 500 MS/s sample clock, 100 kHz sweep trigger). Configure these settings in the DAQ Timing Settings section of the Miscellaneous tab:
DAQ Timing Settings on the Miscellaneous tab
Once a Test Vector is downloaded, DAQ Timing Settings are configured as desired, and Test Vectors are selected as the raw data source (see Pipeline Modes & Subsampling tab), then use the usual GUI or API controls for changing operational modes and pipeline modes of the DAQ, just as if the ADCs were selected as the raw data source like during normal operation.

Quitting the Hardware Control Tool

To exit the Hardware Control Tool and drop existing connections to Axsun devices, simply close the main window by clicking the "x" icon in the upper right corner:
Last modified 5mo ago